A delay chain is a circuit for generating a multi-phased clocking signal and is used in circuits such as delay-lock loops, phase lock loops, and time-to-digital converters. A delay chain may include a plurality of delay cells cascaded in sequence. Each delay cells introduces a nominal delay. Various delay chain designs include delay cells intended to execute identical delays. Generally, however, there is usually a mismatch between delay cells and thus, their delays are different. Differences in delays between cells may be due to such things as manufacturing and material variances. As a result, the sequential outputs of the delay cells are usually not uniformly displaced in time. It is desirable to calibrate out the delay mismatch to alleviate the non-uniformity. Some present methods rely on statistical approaches to calibrate the mismatch. A statistical approach, although useful, demands significant overhead in both circuit area and power consumption.